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PCA9500 8-bit I2C and SMBus I/O port with 2-kbit EEPROM
Product data sheet Supersedes data of 27 Jun 2003 2004 Sep 30
Philips Semiconductors
Philips Semiconductors
Product data sheet
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
PCA9500
DESCRIPTION
The PCA9500 is an 8-bit I/O expander with an on-board 2-kbit EEPROM. The I/O expander's eight quasi bidirectional data pins can be independently assigned as inputs or outputs to monitor board level status or activate indicator devices such as LEDs. The system master writes to the I/O configuation bits in the same way as for the PCF8574. The data for each Input or Output is kept in the corresponding Input or Output register. The system master can read all registers.
FEATURES
* 8 general purpose input/output expander/collector * Drop in replacement for PCF8574 with integrated 2-kbit EEPROM * Internal 256 x 8 EEPROM * Self timed write cycle * 4 byte page write operation * I2C and SMBus interface logic * Internal power-on reset * Noise filter on SCL/SDA inputs * 3 address pins allowing up to 8 devices on the I2C/SMBus * No glitch on power-up * Supports hot insertion * Power-up with all channels configured as inputs * Low standby current * Operating power supply voltage range of 2.5 V to 3.6 V * 5 V tolerant inputs/outputs * 0 kHz to 400 kHz clock frequency * ESD protection exceeds 2000 V HBM per JESD22-A114, * Latch-up testing is done to JESDEC Standard JESD78 which * Package offerred: SO16, TSSOP16, HVQFN16
ORDERING INFORMATION
PACKAGES 16-Pin Plastic SO (wide) 16-Pin Plastic TSSOP TEMPERATURE RANGE -40 C to +85 C -40 C to +85 C exceeds 100 mA 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
The EEPROM can be used to store error codes or board manufacturing data for read-back by application software for diagnostic purposes and is included in the I/O expander package. The PCA9500 has three address pins with internal pull-up resistors allowing up to 8 devices to share the common two-wire I2C software protocol serial data bus. The fixed GPIO I2C address is the same as the PCF8574 and the fixed EEPROM I2C address is the same as the PCF8582C-2, so the PCA9500 appears as two separate devices to the bus master. The PCA9500 supports hot insertion to facilitate usage in removable cards on backplane systems. The PCA9501 is an alternative to the functionally similar PCA9500 for systems where a higher number of devices are required to share the same I2C-bus or an interrupt output is required.
ORDER CODE PCA9500D PCA9500PW
TOPSIDE MARK PCA9500D PCA9500
DRAWING NUMBER SOT162-1 SOT403-1 SOT629-1
16-Pin Plastic HVQFN -40 C to +85 C PCA9500BS 9500 Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging. SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I2C patent. I2C is a trademark of Philips Semiconductors Corporation.
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
PCA9500
PIN CONFIGURATION - SO, TSSOP
A0 1 A1 2 16 VDD 15 SDA 14 SCL 13 WC PCA9500 12 I/O7 11 I/O6 10 I/O5
PIN CONFIGURATION - HVQFN
A1 16 A0 15 VDD 14 SDA 13 12 SCL 11 WC 10 I/O7 9 5 6 7 8 I/O6 I/O5
A2 I/O0 I/O1 I/O2
1 2 3 4
A2 3 I/O0 4 I/O1 5 I/O2 6 I/O3 7 VSS 8
9
I/O4
I/O3
VSS I/O4
SW00902
TOP VIEW Figure 2. Pin configuration - HVQFN
SW02004
Figure 1. Pin configuration - SO, TSSOP
PIN DESCRIPTION
SO, TSSOP PIN NUMBER 1,2,3 4,5,6,7 8 9,10,11,12 13 14 15 16 HVQFN PIN NUMBER 15, 16, 1 2, 3, 4, 5 6 7, 8, 9, 10 11 12 13 14 SYMBOL A0-2 I/O0 to I/O3 VSS I/O4 to I/O7 WC SCL SDA VDD NAME AND FUNCTION Address lines (internal pull-up) Quasi-bidirectional I/O pins Supply ground Quasi-bidirectional I/O pins Active LOW write control pin I2C Serial Clock I2C Serial Data Supply Voltage
BLOCK DIAGRAM
PCA9500
300 k
A0 A1 A2 SCL SDA INPUT FILTER I2C/SMBus CONTROL 8-BIT INPUT/ OUTPUT PORTS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
WRITE pulse READ pulse VDD VSS POWER-ON RESET
WC
EEPROM 256 x 8
SW01074
Figure 3. Block diagram
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
PCA9500
FUNCTIONAL DESCRIPTION
VDD WRITE PULSE 100 A DATA FROM SHIFT REGISTER D FF CI S POWER-ON RESET VSS I/O0 TO I/O7 Q
D FF READ PULSE CI S
Q
DATA TO SHIFT REGISTER
SW00546
Figure 4. Simplified schematic diagram of each I/O
DEVICE ADDRESSING
Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9500 is shown in Figure 5. Internal pullup resistors are incorporated on the hardware selectable address pins.
SLAVE ADDRESS SLAVE ADDRESS
0
1
0
0
A2
A1
A0
R/W
1
0
1
0
A2
A1
A0
R/W
FIXED (a) I/O EXPANDER (b) MEMORY a.
HARDWARE PROGRAMMABLE
FIXED b.
HARDWARE PROGRAMMABLE
SW01075
Figure 5. PCA9500 slave addresses The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected while a logic 0 selects a write operation.
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
PCA9500
CONTROL REGISTER
The PCA9500 contains a single 8-bit register called the Control Register, which can be written and read via the I2C-bus. This register is sent after a successful acknowledgment of the slave address. It contains the I/O operation information.
I/O OPERATIONS (see also Figure 4)
Each of the PCA9500's eight I/Os can be independently used as an input or output. Output data is transmitted to the port by the I/O WRITE mode (see Figure 6). Input I/O data is transferred from the port to the microcontroller by the READ mode (See Figure 7).
SCL
1
2
3
4
5
6
7
8
SLAVE ADDRESS (I/O EXPANDER)
DATA TO PORT
DATA TO PORT
SDA
S
0
1
0
0
A2
A1
A0
0
A
DATA 1
A
DATA 2
A
START CONDITION WRITE TO PORT
R/W
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
DATA OUT FROM PORT t pv
DATA 1 VALID t pv
DATA 2 VALID
SW00548
Figure 6. I/O WRITE mode (output)
SLAVE ADDRESS (I/O EXPANDER)
DATA FROM PORT
DATA FROM PORT
SDA
S
0
1
0
0
A2
A1
A0
1
A
DATA 1
A
DATA 4
1
P
START CONDITION READ FROM PORT
R/W
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM MASTER
STOP CONDITION
DATA INTO PORT
DATA 1 t ph
DATA 2
DATA 3 t ps
DATA 4
SW00549
Figure 7. I/O READ mode (input)
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
PCA9500
Quasi-bidirectional I/Os (see Figure 8)
A quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data direction. At power-on the I/Os are HIGH. In this mode, only a current source to VDD is active. An additional strong pull-up to VDD allows fast rising edges into heavily loaded outputs. These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before being used as inputs.
SLAVE ADDRESS (I/O EXPANDER)
DATA TO PORT
DATA TO PORT
SDA
S
0
1
0
0
A2
A1
A0
0
A
1
A
0
A
P
START CONDITION
R/W
ACKNOWLEDGE FROM SLAVE
I/O3
ACKNOWLEDGE FROM SLAVE
I/O3
SCL
1
2
3
4
5
6
7
8
I/O3 OUTPUT VOLTAGE
I/O3 PULL-UP OUTPUT CURRENT
IOHt
IOH
SW00905
Figure 8. Transient pull-up current IOHt while I/O3 changes from LOW-to-HIGH and back to LOW
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
PCA9500
MEMORY OPERATIONS Write operations
Write operations require an additional address field to indicate the memory address location to be written. The address field is eight bits long, providing access to any one of the 256 words of memory. There are two types of write operations, byte write and page write. Write operation is possible when WC control pin put at a low logic level (0). When this control signal is set at 1, write operation is not possible and data in the memory is protected. Byte Write and Page Write explained below assume that Write Control pin (WC) is set to 0. Byte Write (see Figure 9) To perform a byte write the start condition is followed by the memory slave address and the R/W bit set to 0. The PCA9500 will respond with an acknowledge and then consider the next eight bits sent as
the word address and the eight bits after the word address as the data. The PCA9500 will issue an acknowledge after the receipt of both the word address and the data. To terminate the data transfer the master issues the stop condition, initiating the internal write cycle to the non-volatile memory. Only write and read operations to the Quasi-bidirectional I/O are allowed during the internal write cycle. Page Write (see Figure 10) A page write is initiated in the same way as the byte write. If after sending the first word of data, the stop condition is not received the PCA9500 considers subsequent words as data. After each data word the PCA9500 responds with an acknowledge and the two least significant bits of the memory address field are incremented. Should the master not send a stop condition after four data words the address counter will return to its initial value and overwrite the data previously written. After the receipt of the stop condition the inputs will behave as with the byte write during the internal write cycle.
SLAVE ADDRESS (MEMORY)
WORD ADDRESS
DATA
SDA
S
1
0
1
0
A2
A1
A0
0
A
A
DATA
A
P
START CONDITION
R/W
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
STOP CONDITION. WRITE TO THE MEMORY IS PERFORMED
SW02036
Figure 9. Byte write
SLAVE ADDRESS (MEMORY)
WORD ADDRESS
DATA TO MEMORY
DATA TO MEMORY
SDA
S
1
0
1
0
A2 A1 A0 0
A
A
DATA n
A
DATA n + 3
A
P
START CONDITION
R/W ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
STOP CONDITION. WRITE TO THE MEMORY IS PERFORMED
SW02037
Figure 10. Page Write
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
PCA9500
Read operations
PCA9500 read operations are initiated in an identical manner to write operations with the exception that the memory slave address' R/W bit is set to a one. There are three types of read operations; current address, random and sequential. Current Address Read (see Figure 11) The PCA9500 contains an internal address counter that increments after each read or write access, as a result if the last word accessed was at address n then the address counter contains the address n+1. When the PCA9500 receives its memory slave address with the R/W bit set to one it issues an acknowledge and uses the next eight clocks to transmit the data contained at the address stored in the address counter. The master ceases the transmission by issuing the stop condition after the eighth bit. There is no ninth clock cycle for the acknowledge. Random Read (see Figure 12) The PCA9500's random read mode allows the address to be read from to be specified by the master. This is done by performing a dummy write to set the address counter to the location to be read.
The master must perform a byte write to the address location to be read, but instead of transmitting the data after receiving the acknowledge from the PCA9500 the master reissues the start condition and memory slave address with the R/W bit set to one. The PCA9500 will then transmit an acknowledge and use the next eight clock cycles to transmit the data contained in the addressed location. The master ceases the transmission by issuing the stop condition after the eighth bit, omitting the ninth clock cycle acknowledge. Sequential Read (see Figure 13) The PCA9500 sequential read is an extension of either the current address read or random read. If the master doesn't issue a stop condition after it has received the eighth data bit, but instead issues an acknowledge, the PCA9500 will increment the address counter and use the next eight cycles to transmit the data from that location. The master can continue this process to read the contents of the entire memory. Upon reaching address 255 the counter will return to address 0 and continue transmitting data until a stop condition is received. The master ceases the transmission by issuing the stop condition after the eighth bit, omitting the ninth clock cycle acknowledge.
SLAVE ADDRESS (MEMORY)
DATA FROM MEMORY
SDA
S
1
0
1
0
A2
A1
A0
1
A
P
START CONDITION
R/W
ACKNOWLEDGE FROM SLAVE
STOP CONDITION
SW00556
Figure 11. Current Address Read
SLAVE ADDRESS (MEMORY)
WORD ADDRESS
SLAVE ADDRESS (MEMORY)
DATA FROM MEMORY
SDA
S
1
0
1
0 A2 A1 A0
0
A
A ACKNOWLEDGE FROM SLAVE
S
1
0
1
0 A2 A1 A0 R/W
1
A
P
START CONDITION
R/W ACKNOWLEDGE FROM SLAVE
START CONDITION
ACKNOWLEDGE FROM SLAVE
STOP CONDITION
SW00557
Figure 12. Random Read
SLAVE ADDRESS (MEMORY)
DATA FROM MEMORY
DATA FROM MEMORY
DATA FROM MEMORY
SDA
S
1
0
1
0
A2 A1 A0 R/W
1
A
DATA n
A
DATA n+1
A
DATA n+X
P
START CONDITION
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM MASTER
ACKNOWLEDGE FROM MASTER
STOP CONDITION
SW00558
Figure 13. Sequential Read
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
PCA9500
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
Start and Stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the Start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the Stop condition (P) (see Figure 15).
Bit transfer
One data bit is transferred during each clock phase. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (See Figure 14).
System configuration
A device generating a message is a "transmitter", a device receiving is the "receiver". The device that controls the message is the "master" and the devices which are controlled by the master are the "slaves" (see Figure 16).
SDA
SCL
DATA LINE STABLE; DATA VALID
CHANGE OF DATA ALLOWED
SW00542
Figure 14. Bit transfer
SDA
SDA
SCL S START CONDITION P STOP CONDITION
SCL
SW00543
Figure 15. Definition of start and stop conditions
SDA SCL
MASTER TRANSMITTER/ RECEIVER
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
SW00544
Figure 16. System configuration
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
PCA9500
Acknowledge (see Figure 17)
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked
out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT BY TRANSMITTER NOT ACKNOWLEDGE
DATA OUTPUT BY RECEIVER ACKNOWLEDGE
SCL FROM MASTER S START CONDITION
1
2
8
9
CLOCK PULSE FOR ACKNOWLEDGEMENT
SW00545
Figure 17. Acknowledgment on the I2C-bus
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
PCA9500
TYPICAL APPLICATION Applications
* Board version tracking and configuration * Board health monitoring and status reporting * Multi-card systems in Telecom, Networking, and Base Station
Infrastructure Equipment
* Field recall and troubleshooting functions for installed boards
UP TO 8 CARDS
* General-purpose integrated I/O with memory * Drop in replacement for PCF8574 with integrated 2-kbit EEPROM * Bus master sees GPIO and EEPROM as two separate devices * Three hardware address pins allow up to 8 PCA9500s to be
located in the same I2C/SMBus
I2C
ASIC
I2C
CPU OR C BACKPLANE
I2C
I2C
CONFIGURATION CONTROL
I2C
PCA9500
CONTROL
INPUTS GPIO MONITORING AND CONTROL ALARM LEDs
I2C
EEPROM
CARD ID, SUBROUTINES, CONFIGURATION DATA, OR REVISION HISTORY
SW02003
Figure 18. Typical application A central processor/controller typically located on the system main board can use the 400 kHz I2C/SMBus to poll the PCA9500 devices located on the system cards for status or version control type of information. The PCA9500 may be programmed at manufacturing to store information regarding board build, firmware version, manufacturer identification, configuration option data... Alternately, these devices can be used as convenient interface for board configuration, thereby utilizing the I2C/SMBus as an intra-system communication bus.
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
PCA9500
TYPICAL APPLICATION
VDD VDD SCL SDA MASTER CONTROLLER 10 k 10 k 10 k (optional) VDD SCL SDA I/01 INT I/00 SUBSYSTEM 1 (e.g. temp sensor) 2 k
I/02 GND I/03 PCA9500 I/04 SUBSYSTEM 2 (e.g. counter) RESET
I/05 A2
A Controlled Switch (e.g. CBT device) ENABLE
I/06
A1 I/07 A0
B
VSS
ALARM SUBSYSTEM 3 (e.g. alarm system)
NOTE: GPIO device address configured as 0100100 for this example EEPROM device address configured as 1010100 for this example I/00, I/02, I/03, configured as outputs I/01, I/04, I/05, configured as inputs I/006, I/07, are not used and have to be configured as outputs
VDD
SW01076
Figure 19. Typical application
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
PCA9500
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. SYMBOL VCC VI II IO IDD ISS Ptot PO Tstg Tamb Supply voltage Input voltage DC input current DC output current Supply current Supply current Total power dissipation Total power dissipation per output Storage temperature Operating temperature PARAMETER MIN -0.5 VSS - 0.5 -20 -25 -100 -100 -- -- -65 -40 MAX 4.0 5.5 20 25 100 100 400 100 +150 +85 UNIT V V mA mA mA mA mW mW _C _C
DC ELECTRICAL CHARACTERISTICS
Tamb = -40 to +85 _C unless otherwise specified; VCC = 3.3 V SYMBOL Supply VDD IDDQ IDD1 IDD2 VPOR VIL VIH IOL ILI CI VIL VIH IIHL(max) IOL IOH IOHt CI CO VIL VIH ILI Supply voltage Standby current Supply current read Supply current write Power-on reset voltage LOW-level input voltage HIGH-level input voltage LOW-level output current Input leakage current Input capacitance LOW-level input voltage HIGH-level input voltage Input current through protection diodes LOW-level output current HIGH-level output current Transient pull-up current Input capacitance Output capacitance LOW-level input voltage HIGH-level input voltage Input leakage current Input leakage (pull-up) current VI = VDD VI = VSS VOL = 1 V VOH = Vss VOL = 0.4 V VI = VDD or VSS VI = VSS A0, A1, A2, WC = HIGH 2.5 -- -- -- -- -0.5 0.7VDD 3 -1 -- -0.5 0.7VDD -400 10 30 -- -- -- -0.5 0.7VDD -1 10 3.3 -- -- -- -- -- -- -- -- -- -- -- -- 25 100 2 -- -- -- -- -- 25 3.6 60 1 2 2.4 0.3VDD 5.5 -- 1 7 0.3VDD 5.5 400 -- 300 -- 10 10 0.3VDD 5.5 1 100 V A mA mA V V V mA A pF V V A mA A mA pF pF V V A A PARAMETER CONDITIONS MIN TYP MAX UNIT
Input SCL; input, output SDA
I/O Expander Port
Address Inputs (A0, A1, A2), WC input
NOTES: 1. Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
PCA9500
NON-VOLATILE STORAGE SPECIFICATIONS
PARAMETER Memory cell data retention Number of memory cell write cycles 10 years minimum 100,000 cycles minimum SPECIFICATION
I2C-BUS TIMING CHARACTERISTICS
SYMBOL I2C-bus timing (see Figure 20; Note 2) fSCL tSW tBUF tSU;STA tHD;STA tr tf tSU;DAT tHD;DAT tVD;DAT tSU;STO SCL clock frequency tolerable spike width on bus bus free time START condition set-up time START condition hold time SCL and SDA rise time SCL and SDA fall time data set-up time data hold time SCL LOW to data out valid STOP condition set-up time -- -- 1.3 0.6 0.6 -- -- 250 0 -- 0.6 -- -- -- -- -- -- -- -- -- -- -- 400 50 -- -- -- 0.3 0.3 -- -- 1.0 -- kHz ns s s s s s ns ns s s PARAMETER MIN. TYP. MAX. UNIT
NOTE: 2. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input voltage swing of VSS to VDD.
PORT TIMING CHARACTERISTICS
SYMBOL tpv tps tph PARAMETER Output data valid; CL 100 pF Input data setup time; CL 100 pF Input data hold time; CL 100 pF MIN -- 0 4 TYP -- -- -- MAX 4 -- -- UNIT s s s
handbook, full pagewidth
PROTOCOL
START CONDITION (S)
BIT 7 MSB (A7)
BIT 6 (A6)
BIT 0 LSB (R/W)
ACKNOWLEDGE (A)
STOP CONDITION (P)
t
SU;STA
1 / f SCL
SCL
t
BUF
tr
t
f
SDA
t HD;STA
t
SU;DAT
t
HD;DAT
t
VD;DAT
MBD820
t SU;STO
SW00561
Figure 20.
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
PCA9500
POWER-UP TIMING
SYMBOL tPUR
1
PARAMETER Power-up to Read Operation Power-up to Write Operation
MAX. 1 5
UNIT ms ms
tPUW1
NOTE: 1. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are guaranteed by design.
WRITE CYCLE LIMITS
SYMBOL tWR1 PARAMETER Write Cycle Time MIN. -- TYP. (5) 5 MAX. 10 UNIT ms
NOTE: 1. tWR is the maximum time that the device requires to perform the internal write operation.
Write Cycle Timing
SCL
SDA
8th Bit Word n
ACK tWR Stop Condition Start Condition MEMORY ADDRESS
SW00560
Figure 21.
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
PCA9500
TYPICAL PERFORMANCE CURVES
20 IOH (A) 0 -20 2.5 V -40 -60 2.7 V -80 3.0 V -100 -120 -140 -160 0 0.4 0.8 1.2 1.6 VOH (V) 2.0 2.4 2.8 3.2 3.6 3.3 V 3.6 V Tamb = -40 C
SW02351
Figure 22. VOH versus IOH (Tamb = -40 C)
20 IOH (A) 0 Tamb = 25 C
SW02350
-20 2.5 V -40 2.7 V -60 3.3 V -80 3.6 V 3.0 V
-100
-120 -140 0 0.4 0.8 1.2 1.6 VOH (V) 2.0 2.4 2.8 3.2 3.6
Figure 23. VOH versus IOH (Tamb = 25 C)
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
PCA9500
20 IOH (A) 0 Tamb = 85 C
SW02352
-20 2.5 V -40 2.7 V -60 3.0 V -80 3.3 V 3.6 V
-100 -120
-140 0 0.4 0.8 1.2 1.6 VOH (V) 2.0 2.4 2.8 3.2 3.6
Figure 24. VOH versus IOH (Tamb = 85 C) NOTE: Rapid fall off in VOH at current inception is due to a diode that provides 5 V overvoltage protection for the GPIO I/O pins. When the GPIO I/O are being used as inputs, the internal current source VOH should be evaluated to determine if external pull-up resistors are required to provide sufficient VIH threshold noise margin.
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17
Philips Semiconductors
Product data sheet
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
PCA9500
SOLDERING Introduction
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our IC Package Databook (order code 9398 652 90011). Wave soldering Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: followed by a smooth laminar wave) soldering technique should be used.
* A double-wave (a turbulent wave with high upward pressure * The longitudinal axis of the package footprint must be
parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonally opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
DIP
Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400C, contact may be up to 5 seconds.
SO and SSOP
Reflow soldering Reflow soldering techniques are suitable for all SO and SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C.
2004 Sep 30
18
Philips Semiconductors
Product data sheet
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
PCA9500
SO16: plastic small outline package; 16 leads; body width 7.5 mm
SOT162-1
2004 Sep 30
19
Philips Semiconductors
Product data sheet
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
PCA9500
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
2004 Sep 30
20
Philips Semiconductors
Product data sheet
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
PCA9500
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm
SOT629-1
2004 Sep 30
21
Philips Semiconductors
Product data sheet
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
PCA9500
REVISION HISTORY
Rev _3 Date 20040930 Description Product data sheet (9397 750 14134). Supersedes data of 2003 Jun 27 (9397 750 11682). Modifications:
* Figure 19: resistor values changed to 10 k * "DC characteristics" table on page : add Table note 1. * Added "Typical performance curves" section
_2 _1 20030627 20020927 Product data (9397 750 11682); ECN 853-2369 30018 dated 11 June 2003. Supersedes data of 2002 September 09 (9397 750 10326). Product data (9397 750 10326); ECN: 853-2369 28875 (2002 Sep 27)
2004 Sep 30
22
Philips Semiconductors
Product data sheet
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
PCA9500
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
Level
I
Data sheet status [1]
Objective data sheet
Product status [2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data sheet
Qualification
III
Product data sheet
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2004 All rights reserved. Published in the U.S.A. Date of release: 09-04
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document number:
9397 750 14134
Philips Semiconductors
2004 Sep 30 23

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